EE 469-569 Advanced Digital System Design

Summer 2012

Course Instructor

Course Policy and Syllabus

Master Schedule (Subject to change!)

See below for topics covered by each test, lab, and HW set

Lecture No.	Subject	Book Chapter	Date	HW As'd	Lab As'd	HW Due	Lab Due	Tests
1	Motivation, Time / Freq / Distance	1,2	30-May
2	Ckt. Board and Chassis Design		30-May		Lab A
3	Properties of Logic Gates and Packaging		4-Jun		Lab B
4	Modeling Circuit Boards and Logic Gates	3	6-Jun	HW 1
5	Resistance and Capacitance	4,5	6-Jun
6	Inductance	6	11-Jun
7	Lumped Analysis: Ground Bounce and Ringing		13-Jun	HW 2		HW 1	Lab A
8	Testing and Debugging Boards		13-Jun
10	DFX and Quality Management		13-Jun		Lab C
9	Power Infrastructure: freq. domain (T1 Rvw)		18-Jun	HW 3
	(Test 1)		20-Jun			HW 2		Test 1
11	Transmission Lines -- Z0 and reflections (Lab B)	7	25-Jun	HW 4		HW 3	Lab B
12	Transmission Lines -- Termination, Imperfections	8	25-Jun
13	Transmission Lines -- Lossiness	9	27-Jun	HW 5		HW 4
14	Commercial and Legal Implications (T2 Rvw)		2-Jul	HW 6
	(Test 2)		9-Jul			HW 5		Test 2
15	Project Management and Risk Mitigation		9-Jul		Lab D	HW 6
16	Crosstalk -- NEXT and FEXT	10	11-Jul	HW 7			Lab C
17	Differential Signaling, Even/Odd modes	11	16-Jul	HW 8
18	EMI, EMC, Susceptibility, ESD (T3 Rvw)		16-Jul
	(Test 3)		18-Jul			HW 7		Test 3
19	Clocks: Distribution, Skew, and Jitter		23-Jul			HW 8
20	Final Review and wrap-up		23-Jul				Lab D
	Final Exam (8:00 AM)		24-Jul					Final

Lecture Notes

Downloadable Software for the Course

PSpice -- We will use PSpice to do the homework sets.

ExpressPCB -- Simple board-layout tool. We will use this in Lab A.

Homework Sets

	Homework sets:	Assigned	Due Date
HW 1	Simple SPICE model	6-Jun	13-Jun
HW 2	Simulate ground bounce and ringing	13-Jun	20-Jun
HW 3	Power-system analysis in f domain	18-Jun	25-Jun
HW 4	Simulate unterminated & terminated line	25-Jun	27-Jun
HW 5	Simulate line with cap in middle (right angle, via)	27-Jun	9-Jul
HW 6	Simulate lossy lines	2-Jul	9-Jul
HW 7	Simulate crosstalk	11-Jul	18-Jul
HW 8	Simulate differential signal	16-Jul	23-Jul

Projects / Labs

Labs	Subject	Assigned	Due Date
Lab A	Design circuit board in ExpressPCB	30-May	13-Jun
Lab B	Report on one modern bus	4-Jun	25-Jun
Lab C	DFX / CPK / 6-sigma	13-Jun	11-Jul
Lab D	BOM / COGS / MRP analysis + project Gantt chart / milestones	9-Jul	23-Jul

Test Coverage

Tests	Covered	Date
Test 1	Freq / Time / Distance, Ground Bounce, Ringing	20-Jun
Test 2	Power Distr'n, R, C, L, Transmission Lines	9-Jul
Test 3	Crosstalk, EMI / EMC	18-Jul
Final	Cumulative	24-Jul

Group Assignments:

Group:
1
2
3
4
5
6

About Lab A:

Get the schematic and bill of materials (BOM) from the website. Enter the schematic and lay out a 2-layer circuit board to implement the circuit. You may use the ExpressPCB software if you wish -- it is free and relatively easy to use. Note that the ATmega 168, clock chip, and headers are "through-hole" parts, and so their signals are available on both sides of the PWB. That will help you do the layout. I have created the symbols and layout for the ATmeag 168 and clock chip, available here.

About Lab B:

Each group must select a different bus standard. Each group will report on a different standard.

SATA

PCIe

USB (including USB 3)

DDR3

Gig-E

HDMI

Firewire

The reports must cover these aspects of the bus standard:

Common uses

Topology

Signal levels, Frequency, Rise times, Eye diagram

PWB requirements -- Z0, spacing, etc.

Connector styles

The group should prepare...

Written report: A report that covers the topics listed above for the selected standard

Oral report: A PowerPoint presentation to be delivered in class on the "Due Date" listed above.

Additional Resources

Formulas, Constants, and Symbols -- Used in the lectures

Power Supply Handout -- Describes how to size power-supply components for continuous coverage in the frequency domain

Impedance Trace Calculator -- From the EMC Lab at the Missouri University of Science and Technology (formerly Missouri-Rolla)