| Date | Work On / Demonstrate | Due * |
| 18-Jan | ||
| 25-Jan | Experiment 1 | |
| 1-Feb | Experiment 2 | Experiment 1 |
| 8-Feb | Experiment 3 | Experiment 2 |
| 15-Feb | Experiment 4 | Experiment 3 |
| 22-Feb | Experiment 5 | Experiment 4 |
| 1-Mar | Experiment 6 | Experiment 5 |
| 22-Mar | Experiment 7 | Experiment 6 |
| 29-Mar | Experiment 8 | Experiment 7 |
| 5-Apr | Experiment 9 | Experiment 8 |
| 12-Apr | Experiment 10 | Experiment 9 |
| 19-Apr | Lab Final? | Experiment 10 |
| 26-Apr | ||
| 3-May | ||
*The "due date" is the date that the report is due. The lab should be demonstrated to the instructor or TA the week before.
| Group 1 | Mukura, Lazarus L. | Britt, Justin N. | |
| Group 2 | Durant, Isis T. | Dunn, Michael C. | Walden, Michael C. |
| Group 3 | Ford, Khaleahcia L. | Aguila, Ma Victoria Y. | Kamolzoda, Umed |
| Group 4 | Lu, Hai V. | Alalwani, Mohammed A. | |
| Group 5 | Gaffney, Aaron J. | Baldwin, Aaron L. | |
| Group 6 | Massey, Kyle R. | Tobin, Ryan | Martin, Daniel B. |
| Group 7 | Florian, Timothy S. | Rinehart, Robert R. | Stewart, Jonathan |
1. Use the "Word Generator" to create the inputs to your circuit. I found it easiest to put the generator on "cycle" and then select Pattern -> Up Counter to get the generator to create a repeating bit pattern that exercises all input combinations.
2. Start with the word generator output bit labeled 0 and work your way up. The schematic looks neater if you flip the generator horizontally, which puts bit 0 on the right side of the generator.
3. The components are labeled alphabetically, not numerically. Also, an OR gate is a 7432. (That one took a while for me to remember!) So you have to scroll down quite a bit to find the 7432.
4. Route all the inputs and outputs to a logic analyzer. This lets you see the inputs and outputs side-by-side.
5. I found it helpful to click on the input and output wires and give them useful names. For example, for D=AB+C, I labeled the inputs A, B, and C, and the output D. That way the logic analyzer output matches the problem you are solving.
6. A screen capture of the schematic will be a good way to document your design when you write a report.
7. If you want a truth-table output instead of watching a logic analyzer trace, replace the word generator with a "logic converter". Wire the circuit inputs to the converter inputs (bank of eight nodes) and the circuit output to the converter output (single node on the right). Press the "logic gate to truth table" icon to produce the circuit's truth table. Again, a screen capture is a good way to document that your circuit worked correctly in simulation.
1. On computers in the ECE department labs
2. Online: I Googled and found a student version for $34 - 35 here and here. You can also get a version directly from National Instruments for $40 here which supports more components and has a larger parts library.