| HW Sets | Assigned | Due date | |
| 1 | SPECint, Pipelining | 31-Jan | 9-Feb |
| 2 | MMU | 16-Feb | 1-Mar |
| 3 | Cache | 1-Mar | 20-Mar |
| 4 | Superscalar + Cache + MMU | 29-Mar | 10-Apr |
| 5 | Branch and target prediction | 3-Apr | 17-Apr |
| 6 | Processor report | 5-Apr | 1-May |
| 7 | Memory hierarchy | 17-Apr | 26-Apr |
| 8 | Parallel processing | 26-Apr | 3-May |
Lecture 4: MIPS Instructions and MMU
Lecture 6: Superscalar and VLIW
Lecture 9: Parallel Processing
Some of the lectures will make reference to the MIPS processor. Rather than having you buy an entire book, I will summarize the MIPS information that you need in this area.
MIPS Instruction-Set Reference
MIPS Supplemental Information -- Information about instructions, pipelining, MMU, and Caches
Some of the lectures will make reference to Intel architectures. The primary source of information is Intel's own IA-32 manual:
Intel IA-32 Software Developer's Manual Volume 1
Some of the homework sets will count as "projects"
| 1 | Kakani, Sainath | Nalluri, Surendra | Chevula, Sandeep Reddy | Gudluru, Sanjay | |
| 2 | Attan, Abilash | Nori, Balasubramanyam | Sirga, Sai K. | Sreenivasulu, Rajesh C. | |
| 3 | Kucherlapati, Swetha | Yalamanchili, Sri Harsha | Kandula, Preethi | Durgempudi, Sravya | |
| 4 | Aluri, Sandeep Raja | Deegutla, Sai Brahma Chary | Kuchi, Mahesh | Vanka, Manikanta Sathya P. | |
| 5 | Mohd, Khaja A. | Kotaprolu, Koutilya Raghu R. | Poloju, Satya Nagendra P. | Thummaluru, Harikesh Reddy | |
| 6 | Habib, Md. Habib U. | Chy, Md. N. | Paheding, Sidike | Mishra, Fnu S. | Sajid, Towsif A. |
| Tests | Subjects |
Date |
| Test 1 | Pipelining | 14-Feb |
| Test 2 | MMU and Cache | 22-Mar |
| Test 3 | Instruction Fetch | 19-Apr |
| Final |